Metal process

Troubleshooting and Investigating Virtual 3D NAND Processes

Modern semiconductor processes are extremely complicated and involve thousands of individual, interacting process steps. During the development of these process steps, obstacles and barriers are often encountered in the form of unforeseen negative interactions between upstream and downstream process modules. These obstacles can create a long delay in the development cycle and increase costs. In this article, we will discuss a solution to this problem using the Design of Experiments (DOE) capabilities found in SEMulator3D.

When manufacturing 3D NAND replacement gate memory devices, one of the key process modules involves forming the metal gates and wordlines in the memory cell. The process begins when a stack of hundreds of alternating layers (levels) of silicon dioxide and sacrificial silicon nitride are deposited on the substrate. Memory holes are then masked and etched through the stack in an array of minimum spaced holes. Each sacrificial layer of silicon nitride, which will become the word line, now looks like a slice of Swiss cheese. Sidewall profile control is difficult during these processing steps, due to the high aspect ratio in the etching process and the extreme depth required for the memory cell holes. Deviations such as bending, bending and twisting may occur during the engraving process. The memory cell hole diameter and hole spacing can vary up to 25% from the top of the stack to the bottom of the stack. After the memory cell materials are deposited into the memory cell holes, a series of long, narrow slotted trenches are masked and etched into the outer edges of the block. This second etch exposes the sacrificial silicon nitride in the sidewall of the split trench. The silicon nitride layers are then etched laterally from the edge towards the middle until they are completely removed. [1] A coating of refractory compound and a conductive metal are then deposited to fill the empty space from the outside towards the middle of the layers of silicon nitride. This process forms the metal gate memory cells and wordlines. [2] The distance between the outer memory cell hole and the inner edge of the slotted trench is called the rail distance (Figure 1). The rail provides a low resistance conduction path along the outer edges of the wordline. Word lines are very long and usually take up the entire length of a block of memory. Wordline resistance must be tightly controlled to maintain the desired memory switching speed.

Fig. 1: Top-down view of experimental runs of the virtual model. Each run (A, B and C) has different experimental conditions. A) Large memory cell hole size, no word line rails and voids enabled in the model. Gaps in word lines are shown in red, with the gaps creating a pinch caused by the small distance between the memory cell holes. B) Large memory cell hole size, word line rail nominal distance and voids disabled in the model. C) Nominal memory cell hole size, nominal word line rail distance. The nominal distance of the word line rails is shown in image C.

We recently used a SEMulator3D model to better understand the factors impacting wordline resistance in 3D NAND. Our study indicated that the resistance of the 3D NAND wordline was much higher than the calculated resistance that would be expected solely due to the elimination of conductive material in the holes of the memory cell. Our study indicated that voids formed when removing and replacing sacrificial silicon nitride with conductive metal, which added to the resistance of the wordline. SEMulator3D virtual models revealed that if the memory cell holes were too large or the spacing between the holes was too narrow, the lateral deposition path to the interior regions of the wordline would be pinched and form voids in the conductive metal (Figure 2).

Fig. 2: SEMulator3D virtual model showing the edge of a word line in a three-plane cross-section. The metal conductor fill does not continue beyond the pinch from the edge of the slotted trench to the center of the wordline. Electric current will only be conducted in the liner from the center of the word line to the pinch.

We ran 200 virtual model experiments using our SEMulator3D process model, varying the memory cell hole diameter, rail distance, and vacuum tracking. The word line resistance was simulated using the electrical analysis package SEMulator3D. Wordline resistance was then extracted from the virtual model experiments, and the percentage increase in resistance was plotted against rail distance, memory cell hole increase, and vacuum tracking (Figure 3).

The effect of forming voids on the strength of the word line can be seen in Figure 3. If you compare the increase in strength of the word line without voids (red line) to the case where voids are present (blue line), the effect of voids is easily visible. The presence of voids increases the resistance of the word line by 55%, regardless of the size of the memory hole. Increasing the outer rail distance can reduce the effect of memory cell hole size on wordline resistance by 200% and reduce the effect of void inclusion on wordline resistance. word line to a negligible increase. The results show that the resistance of the word lines increases with the size of the memory hole.

Fig. 3: Increase in Wordline resistance (in percentage) as a function of the increase in the diameter of the memory cell hole (in percentage) and the distance between the rails (nm). The red line shows the result of including the word line gaps in the model (TRUE) and the blue line removes the word line gaps and fills them (FALSE).

As the rail distance approaches zero, more current is forced to flow through the inner region of the wordline. As the size of the memory hole increases, the voids increase in size and reduce the volume between the low-resistance conductive metal and the higher-resistance refractory compound lining (Figure 4). When the distance between the wordline rails is preserved, the dependence of wordline resistance on memory hole size and metal voids is minimized.

Fig. 4: Top-down view of current density from virtual model experiment runs. Each experimental setup (shown in images A, B, and C) has different experimental treatments (refer to Figure 1 for treatment descriptions). Image A: The rail is not continuous, causing current to flow inside the word line. Image B: The size of the memory hole is the same as in Image A, but the wide rail allows current to flow along the outer edges of the word line. Image C: A nominal memory cell hole size is shown. In this case, the nominal distance of the wordline rails supports a more uniform current density pattern.

Using SEMulator3D Void Tracking, the virtual model was able to predict the effect of a void on wordline resistance, independent of the size of the memory hole. In real-world silicon wafer processing, it’s nearly impossible to create an experiment where you decouple vacuum formation and memory cell hole size during 3D NAND development. In SEMulator3D, experiments that would be difficult or impossible to perform in a fab become possible.

In conclusion, SEMulator3D process modeling was used to reproduce a 3D NAND replacement gate wordline formation process. We have learned that the upstream memory cell hole modulus can negatively impact the downstream wordline forming modulus and create an extreme increase in wordline resistance. Using the virtual model, we were able to simulate the issues between the upstream and downstream modules and conduct experiments to determine a potential solution (in our case, the solution would involve a layout change). SEMulator3D process modeling can identify process and layout issues early in development without substantial silicon wafer experimentation, reducing development delays, wafer manufacturing costs, and time to market .

References:

  1. J. Handy, “An Alternative Kind of Vertical 3D NAND String”, Jim Handy, Objective Analysis, on Semiconductor Memories, November 8, 2013.
  2. A. Goda, “Recent advances in 3D NAND flash technologies”, Electronics 2021, 10(24), 3156.

Brett Lowe

Brett Lowe

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Brett Lowe is leader of the semiconductor process and integration team at Coventor, a Lam research company. He has worked in the development of semiconductor technology for over 35 years. He started his career at Philips Semiconductors, where he worked in manufacturing and process development as a process engineer in the areas of photolithography, dry etch and wet process. He then spent eight years at Zilog, working on unit process development. Later, Brett joined Micron Technology, where he worked in DRAM and 3D NAND process development and integration. At Coventor, his focus is to support enterprise customers with their 3D semiconductor process modeling and technology development requirements.