Metal process

Intel Reports Good Progress on Intel Process Node 4 at IEEE Symposium

This week, Intel is presenting five papers at the IEEE 2022 Symposium on VLSI Technology and Circuits (VLSI) that outline the company’s progress on Intel 4, the semiconductor processing technology formerly known as 7nm. Intel 4 is a transition process for Intel. It is the first Intel process node that uses EUV (extreme ultraviolet, i.e. soft X-ray) lithography instead of deep UV immersion lithography. Advancements in the Intel 4 process support Moore’s Law by doubling the achievable transistor density compared to Intel 7, the process node formerly known as 10nm Enhanced Super Fine (10ESF). The Intel 4 process offers a 20% performance boost over chips made with the Intel 7 process while operating at the same power levels. Alternatively, you can get a 40% power reduction with Intel 4 at the same level of performance achieved by the previous process node.

Intel has been on the back of the competition for the past few years as Intel TD (Technology Development) has postponed the use of EUV lithography longer than it should have. The idea was to delay the use of expensive EUV steppers as long as possible in order to minimize manufacturing costs. By trying to stick with immersion lithography for just one more node, Intel 7, Intel lost performance parity with its major manufacturing competitors. Now the company is all on EUV thanks to Pat Gelsinger’s aggressive stance. Intel 4 will be the company’s first production node to fully adopt EUV.

Ben Sell, Vice President of TD at Intel, is lead author of one of five Intel 4 VLSI Symposium papers, titled “Intel 4 CMOS Technology Featuring Advanced FinFET Transistors Optimized for High-Density, High-Performance Computing” . In a pre-event presentation, Sell said that in addition to reducing feature size, Intel 4 uses EUV to simplify process technology by reducing the complexity and cost of creating each on-chip layer.

With the feature sizes drawn, deep UV immersion lithography requires a multi-pattern to achieve the desired feature density. This is because the sizes of the features drawn are much smaller than the wavelengths of light used. For the Intel 4 process, immersion lithography would require exposing the wafer through five different masks just to create one layer, while EUV only requires one mask thanks to the much shorter wavelengths of light used. So even though an EUV process layer costs more than one created with immersion lithography, due to the immense costs of acquiring and operating an EUV stepper, the cost of an EUV process layer is less than the five passes needed to do the same thing. chip layer with immersion lithography.

The figure below summarizes some of the scaling improvements of Intel 4 over Intel 7:

As shown in the figure, individual characteristics – including contacted gate pitch, fin pitch, and interconnect pitch – have all decreased. Additionally, a previously announced innovation for this process node appears as hatched pink rectangles in the figure above. These rectangles represent “dummy gates”, which are needed to electrically isolate adjacent FinFETs. With the transistor orientation shown in the graph above, the dummy gates separate the left and right positioned FinFETs. Previous Intel process nodes required a pair of dummy gates per transistor, so there were two dummy gates interposed between each FinFET. For Intel 4, adjacent transistors share a dummy gate, halving the number of bulky splitters.

Another major factor in the size reduction is due to the use of three fins per FinFET transistor for the Intel 4 process versus four fins per transistor for the Intel 7 process. (The fins appear as horizontal gray rectangles in the figure above.) Normally, using fewer and smaller fins would degrade the performance of the FinFET because, other things being equal, fewer and finer fins increase the resistance of the transistor channel. Ideally, this resistance should be as low as possible.

However, Sell explained that Intel 4 reduces the number of fins needed per transistor by using “enhanced copper” (cobalt-coated copper) to reduce trace impedance in the lower metal signal layers of the chip. Along with the additional capacity reduction resulting from scaling, Intel was able to reduce the number of fins per transistor in the Intel 4-cell library without sacrificing performance. The net result of these innovations is to double the number of transistors per square millimeter for chips made with Intel 4 compared to Intel 7. Doubling the number of transistors from node to node is the original definition of the law of Moore.

Sell ​​said Intel Foundry Services (IFS) customers will have access to the Intel 4 process, but IFS is really focused on the follow-on process node, Intel 3. He also said the chips developed for the Intel 4 process node would easily port to Intel 3, by design. Intel will use even more EUV lithography steps in the Intel 3 process and create a denser high-performance cell library specifically for this process node.

However, the Intel Process Node 3 itself is an intermediate step. Intel 20A, the first of the company’s “Angstrom Era” nodes, will ditch aging FinFETs in favor of even more three-dimensional RibbonFET transistors, which other semiconductor makers call GAA (gate all around) transistors. RibbonFETs will again greatly increase transistor density by stacking multiple transistor channels (ribbons) vertically on top of each other instead of arranging the channel fins side by side as is the case with FinFETs.

RibbonFETs exhibit improved transistor performance over FinFETs because the RibbonFET gate completely surrounds the channel. FinFET gates only contact the channel on three of the four sides. Therefore, RibbonFET gates better control the current flow through the transistor, which results in better performance. For reference, much older planar FET gates only contacted one of the four sides of the transistor channel, so FinFETs were a real improvement when they first appeared in production a decade ago.

Intel 20A will also be the company’s first process node to move the on-chip power distribution network (PDN) from the top of the chip to the bottom of the chip – the backside of the wafer – which is expected to significantly reduce impedances and improve the performance of PDN while simplifying signal routing on the upper metal layers of the chip by freeing up more space for signal wires in the metal stack. Intel dubbed this back PDN technology “PowerVia”, which is a more expensive approach to creating a PDN because it requires the creation of nano TSVs (through-silicon vias) in the wafer. Innovations such as RibbonFETs and PowerVia add process steps and therefore increase the manufacturing cost per wafer, but this is the price to pay to keep Moore’s Law alive.

Sell ​​said Intel’s Process 4 will be ready for production in the second half of 2022. This process node is associated with Intel’s 14.eThe Gen 2 Meteor Lake client processor architecture, which is expected to appear as production chips in the second or third quarter of 2023. Intel will discuss Meteor Lake at the upcoming Hot Chips 34 conference in August. The Intel Process Node 4 will also be used to manufacture compute tiles (chiplets) for the company’s Granite Rapids processors, which are intended for data center servers.