Metal process

Apple could be the first to use TSMC’s 3nm chip process for M2 Pro

Apple’s 2022 MacBook Pros could house the new M2 Pro and M2 Max chipsets made with TSMC’s latest 3nm manufacturing processaccording to a new report.

TSMC, the world’s largest semiconductor contract manufacturer, has steadily developed its 3nm production process. According to Business hoursApple could be the first customer to get their hands on these chips.

The report notes that Apple will use 3 nm slices for the first time in the second half of 2022, likely for its M2 Pro chipsets. Coming versions built on the 3nm process could include the iPhone-specific A17 chipset, as well as a future third-generation M-series.

Business hours also reported separately that TSMC will begin mass production of its 3 nm slices in September. The report adds that the initial yield will be higher than when TSMC moved to 5nm processes.

Compared to previous chip manufacturing processes, semiconductors made using the 3nm process could bring increased energy efficiency and performance to Apple devices.

2 mentions of process, then wafer, return to process, then wafer and return to process = 4 mentions of process including title against 2 wafers.

3nm is not a wafer. It’s a process. TSMC is able to accelerate its process technology to keep Apple firmly in its camp as well as many other chip design companies.

Technically, of course, the expression “3nm” is indeed a process. Anyway “3nm” is unfortunately only a marketing expression anyway.

I can only assume that the AI ​​being well aware that this is a [manufacturing, production] treat applied to [chipsets, releases, semiconductors].
I can only assume the AI ​​assumed it could safely use the one word slice shortcuts rather than multi-word phrases, assuming most readers here wouldn’t confuse the issue. So…no problem.

There is also no industry-wide agreement on the definition of a 3nm node (emphasis mine):

The term “3 nanometers” has unrelated to any real physical feature (such as grid length, no metal or no grid) transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node should have contact 48 nanometer grid pitch and a tighter one 24 nanometer metallic pitch. However, in real-world business practice, “3nm” is mostly used as a marketing term by individual microchip manufacturers to refer to a new and improved generation of silicon semiconductor chips in terms of increased transistor density (this is i.e. a higher degree of miniaturization), increased speed and reduced power consumption.

It’s just a number they use from their previous process to indicate some reduction in node geometry of different transistor technologies.
Full disclosure, I also didn’t know that until I watched it now and I’m a little bummed I thought it actually meant full size.

edited August 19